Open to work
Hello, I'm
Sihang Wu
Analog/Mixed-Signal IC Design Engineer
Focused on PLL/DLL design, system modeling, and high-performance circuit implementation.
Education
A timeline of my academic background.
M.Sc. Communication and Electronics Engineering
10/2023 - 04/2026Technical University of Munich
Focused on analog/mixed-signal IC design, PLL/DLL systems, and circuit modeling.
B.Sc. Electrical and Electronic Engineering
2020 - 2023University of Duisburg-Essen
Part of a dual-degree program with Zhengzhou University, focused on electronics and communication systems.
B.Sc. Electrical and Information Engineering
2018 - 2020Zhengzhou University
Dual-degree program in collaboration with University of Duisburg-Essen, covering electronics, signal processing, and communication systems.
Projects
Selected projects showcasing my technical skills.
Work Experience
My professional and research experience.
Embedded Systems & Bionic Skin Research Assistant
08/2025 - 04/2026Technical University of Munich | Institute of Cognitive Systems
Developed embedded hardware systems based on hexagonal MCU modules. Responsible for FPC integration and system testing under Linux environments, ensuring system stability and functionality.
DLL Circuit & Layout Design Research Intern
02/2025 - 08/2025Technical University of Munich | Institute of Circuit Design
Designed a full DLL system in 22nm FDSOI, including sampling signal generation, sampling circuits, and VCDL modules. Completed layout design with over 35 metal layers while considering parasitic effects and reliability.
Software Development Support Intern
02/2023 - 08/2023Huawei (Germany Headquarters) | European Service Operations Center
Developed internal tools and automated workflows using Python and HTML, including batch data processing and user behavior tracking. Improved efficiency by over 300%, significantly reducing manual workload. Gained experience in version control (Git) and containerized deployment (Docker).
Tech Stack
MATLAB
Python
OpAmp
SarADC
Bandgap
PLL
DLL
German & English
Cadence Virtuoso
VHDL
Calibre(DRC/LVS/PEX)
MATLAB
Python
OpAmp
SarADC
Bandgap
PLL
DLL
German & English
Cadence Virtuoso
VHDL
Calibre(DRC/LVS/PEX)